C# basic code using functions | MODERN PROGRAMMING LANGUAGE

DATA LOGIC DESIGN

PARALLEL REGISTERS

 Registers:  

 †A register is a memory device that can be used to store more than one bit of information.

 †A register is usually realized as several flip-flops with common control signals that control the movement of data to and from the register.

•                   Common refers to the property that the control signals apply to all flip-flops in the same way.
• A register is a generalization of a flip-flop. Where a flipflop stores one bit, a register stores several bits.
• The main operations on a register are the same as for any storage devices, namely.
• Load or Store: Put new data into the register.
• Read: Retrieve the data stored in the register (usually without changing the stored data)

Control Signals:

•   When they are asserted, they initiate an action in the register.
• Asynchronous Control Signals cause the action to take place immediately.
•  Synchronous Control Signals must be asserted during a clock assertion to have an effect Examples 
• On the following three registers, which control signals are asynchronous and which are synchronous? How are the control signals asserted?

 Verilog description of previous two registers:
 module reg2 (CLK, CLR, LD, OE, D, Q);
 parameter n = 4;
 input CLK, CLR, LD, OE;
input [n-1:0] D;
 output [n-1:0] Q;
 reg [n-1:0] IQ, Q;
 integer k;
 always @(posedge CLK)
 if (CLR) IQ <= 0;
 else if (LD) IQ <= D;
 always @(OE)
if (OE) Q = IQ;
 else Q = 'bz;
 endmodule

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Parallel Load Register

Introduction

A CPU consists of registers. Registers on modern CPUs usually store 32 bit or 64 bits. Registers are made from flip flops.

We're going to look at two ways to make a parallel-load register. A parallel-load register has two basic operations, which are summarized by the following table.

c	Operation
0	Hold
1	Parallel Load (z31-0 = x31-0)

Here's a black box diagram for a parallel load register.

A 32 bit register has 32 bits of data input, x_31-0. It also has 32 bits of output, which is labelled, z_31-0.

There's also a clock input. The register can only be updated at positive clock edges. If c = 0 (at the positive clock edge), then the output of the register is unchanged. If c = 1 (at the positive clock edge), x_31-0, is loaded in parallel, and those 32 bits are output as z_31-0.

Implementing a 4-bit parallel load register with D flip flops

Implementing a 32-bit register is like implementing a 4-bit parallel load register, except with more flip flops. So, we'll do it with 4 flip flops, instead. (Although, by the same reasoning, we could do it with, say, 2 flip flops).

Since we need to store 4 bits, we'll need 4 flip flops. Here's the initial diagram.

At this point, we need to figure out how to make a choice between two options: we either want to hold, or we want to parallel load.

What combinational logic device can we use that allows us to pick between one of many different inputs (or in this case, between one of two inputs)? We should use a 2-1 MUX!

For the "0" input, we want to hold the value. What does that mean? Each flip flop is currently outputting a bit. We want to maintain that same value.

How can we do that with a D flip flop? Recall that a D flip flop reads in the value of D, and makes that the output, Q. If we want to have the output stay the same, we need to feed back the output back into the input, through input 0 of the MUX.

When c = 1 we want to parallel load the input. We accomplish this by feeding in the input x_3-0 into the "1" input of the 2-1 MUX.

The circuit isn't quite complete. We should add the clock and the control input, as well.

The control input is drawn in a "cheating" way. I draw the line going in at the top MUX, and being drawn "straight through" to the other MUXes. You can choose to draw it this way, if you want, or draw it less ambiguously.

Implementing a 2-bit parallel load register with T flip flops

Now, let's implement a parallel load register with T flip flops, instead. To save on space, we'll use 2 bits instead of 4. It should be easy to convert it to 4 bits if necessary.

The first question is how to "hold" using T flip flops. For D flip flops, we did that by feeding the output of the D flip flop back into the input (through the MUX).

We don't want to feed the output back, because that's not how T flip flops work (try to figure out happens if you do feed it back). Recall the two operations of a T flip flop: hold and toggle. You already have a way to "hold" the value. Input the value 0 into the T input!

The hard part is to make a T flip flop parallel load. It's quite easy to do it for D flip flop, since all you do is feed in the input directly to D.

So what does it mean to parallel load? It means to get a flip flop to output the value of x. So, let's think about what that means. Suppose the flip flop current outputs 1, and we want to parallel load 0. This means, we need to toggle the output, so that it changes the output from 1 to 0.

Let's come up with a table to list out all the possibilities.

What we want to load (x)	What is currently being output (q)	What we need to do (T)
x = 0	q = 0	HOLD (T = 0)
x = 0	q = 1	TOGGLE (T = 1)
x = 1	q = 0	TOGGLE (T = 1)
x = 1	q = 1	HOLD (T = 0)

We can derive a Boolean expression for T. If you look carefully, it's just the XOR of x and q.

  T = x XOR q

Here's the circuit:

Variations

If you want to work on a similar problem, you can add features to the parallel load register. For example, here's an expanded table.

c1c0	Operation
00	Hold
01	Parallel Load (z31-0 = x31-0)
10	Logical Shift Left 1 bit
11	Logical Shift Right 1 bit

This requires a 4-1 MUX.

Summary

A CPU relies on a set of registers stored in a register file. These registers can be as simple as the parallel load register shown above, or they can have as many functions as you want.

A parallel load register either holds the value of the outputs, or parallel loads the inputs to make them outputs. They can be designed with D or T flip flops, although it's easier to use D flip flops.